pipelining

On Tue, 06 Sep 2005 03:35:47 -0700, Greenhorn wrote:

> Hi,
> I have read that pentium pro uses 3 piplines, does that mean that all
> the stages (are they 6?) can execute two instructions simultaneously,
> so it would be 6 stage pipeline (and each stage again capable of
> executing 3 instructions simulataneously)

I'm not quite sure what you're asking but, at least theoretically a
processor can execute one insteruction per pipeline stage per pipeline.
That is, each stage of each pipeline can contain *part* of a completed
instruction. A processor can, at best, complete one instruction per
pipeline per cycle.

The above is further limited by the number of
decode/issue/dispatch/completion slots, as well. Think of the pipeline as
it's namesake:

- A pipe can hold so much water; length (i.e. number of pipeline stages).
- More parallel pipes can hold more; width (i.e. number of pipelines
execution units).
- There is an inlet valve (decode/issue/dispatch width)
- And an outlet valve (completion)

The maximum amount of water (instructions) that can be in the pipe
(number of instructions in execution) is the length of the pipeline(s)
times the number of pipelines. The maximum number that can be executed
per clock is limited by the smaller of inlet valve, number of pipes, or
outlet valve.

--
Keith
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